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precision picoampere input current quad operational amplifier op497 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1991C2009 analog devices, inc. all rights reserved. features low offset voltage: 75 v maximum low offset voltage drift: 1.0 v/c maximum very low bias current 25c: 150 pa maximum ?40c to +85c: 300 pa maximum very high open-loop gain: 2000 v/mv minimum low supply current (per amplifier): 625 a maximum operates from 2 v to 20 v supplies high common-mode rejection: 114 db minimum applications strain gage and bridge amplifiers high stability thermocouple amplifiers instrumentation amplifiers photocurrent monitors high gain linearity amplifiers long-term integrators/filters sample-and-hold amplifiers peak detectors logarithmic amplifiers battery-powered systems general description the op497 is a quad op amp with precision performance in the space-saving, industry standard 16-lead solc package. its combination of exceptional precision with low power and extremely low input bias current makes the quad op497 useful in a wide variety of applications. precision performance of the op497 includes very low offset (<50 v) and low drift (<0.5 v/c). open-loop gain exceeds 2000 v/mv ensuring high linearity in every application. errors due to common-mode signals are eliminated by its common- mode rejection of >120 db. the op497 has a power supply rejection of >120 db which minimizes offset voltage changes experienced in battery-powered systems. the supply current of the op497 is <625 a per amplifier, and it can operate with supply voltages as low as 2 v. the op497 uses a superbeta input stage with bias current cancellation to maintain picoamp bias currents at all temperatures. this is in contrast to fet input op amps whose bias currents start in the picoamp range at 25c but double for every 10c rise in temperature to reach the nanoamp range above 85c. the input bias current of the op497 is <100 pa at 25c. pin connections out a 1 ?in a 2 +in a 3 v+ 4 out d 16 ?in d 15 +in d 14 v? 13 +in b 5 ?in b 6 out b nc 7 +in c 12 ?in c 11 out c nc 10 8 9 op497 nc = no connect 00309-001 figure 1. 16-lead wide body soic (rw-16) out a 1 ?in a 2 +in a 3 v+ 4 out d 14 ?in d 13 +in d 12 v? 11 +in b 5 ?in b 6 out b 7 +in c 10 ?in c 9 out c 8 op497 00309-002 figure 2. 14-lead pdip (n-14) 1k 100 10 +i b i os temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 v s = 15v v cm = 0v input current (pa) 0 0309-003 ?i b figure 3. input bias, offset current vs. temperature combining precision, low power, and low bias current, the op497 is ideal for a number of applications, including instrumentation amplifiers, log amplifiers, photodiode preamplifiers, and long- term integrators. for a single device, see the op97 data sheet, and for a dual device, see the op297 data sheet.
op497 rev. e | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? pin connections ............................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 4 ? thermal resistance ...................................................................... 4 ? esd caution .................................................................................. 4 ? typical performance characteristics ............................................. 5 ? applications information .............................................................. 10 ? ac performance ......................................................................... 10 ? guarding and shielding ........................................................... 11 ? open-loop gain linearity ....................................................... 11 ? applications circuit ....................................................................... 12 ? precision absolute value amplifier ......................................... 12 ? precision current pump ............................................................ 12 ? precision positive peak detector .............................................. 12 ? simple bridge conditioning amplifier ................................... 12 ? nonlinear circuits ...................................................................... 13 ? outline dimensions ....................................................................... 14 ? ordering guide .......................................................................... 15 ? revision history 2/09rev. d to rev. e deleted 14-lead cerdip ............................................. throughout changes to features section and general description section ................................................................................................ 1 delete military processed devices text, smd part number, adi part number table, and dice characteristics figure ......... 3 changes to table 1 ............................................................................ 3 changes to absolute maximum ratings section ......................... 4 changes to figure 12 ........................................................................ 6 changes to figure 18 and figure 19 ............................................... 7 changes to figure 26 and figure 28 ............................................... 8 deleted op497 spice macro-model section ............................... 10 changes to applications information section ............................ 10 moved figure 33 ............................................................................. 10 deleted table i. op497 spice net-list....................................... 11 changes to open-loop gain linearity section and figure 35 .......................................................................................... 11 changes to figure 40 ...................................................................... 13 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 11/01rev. c to rev. d edits to pin connection headings .................................................. 1 deleted wafer test limits ................................................................ 3 edits to absolute maximum ratings .............................................. 5 edits to outline dimensions ......................................................... 16 edits to ordering guide ................................................................ 17
op497 rev. e | page 3 of 16 specifications t a = 25c, v s = 15 v, unless otherwise noted. table 1. f grade g grade parameter symbol condition min typ max min typ max unit input characteristics offset voltage v os 40 75 80 150 v ?40c +85c 70 150 120 250 v average input offset voltage drift tcv os t min ? t max 0.4 1.0 0.6 1.5 v/c long-term input offset voltage stability 0.1 0.1 v/month input bias current i b v cm = 0 v 40 150 60 200 pa ?40 t a +85c 60 200 80 300 pa average input bias current drift tc ib ?40 t a +85c 0.3 0.3 pa/c input offset current i os v cm = 0 v 30 150 50 200 pa ?40 t a +85c 50 200 80 300 pa average input offset current drift t c i os 0.3 0.4 pa/c input voltage range 1 ivr 13 14 13 14 v t min ? t max 13 13.5 13 13.5 v common-mode rejection cmr v cm = 13 v 114 135 114 135 db t min ? t max 108 120 108 120 db large signal voltage gain a vo v o = 10 v, r l = 2 k 1500 4000 1200 4000 v/mv ?40 t a +85c 800 2000 800 2000 v/mv input resistance differential mode r in 30 30 m input resistance common mode r incm 500 500 g input capacitance c in 3 3 pf output characteristics output voltage swing v o r l = 2 k 13 13.7 13 13.7 v r l = 10 k, t min ? t max 13 14 13 14 v r l = 10 k 13 13.5 13 13.5 v short circuit i sc 25 25 ma power supply power supply rejection ratio psrr v s = 2 v to 20 v 114 135 114 135 db v s = 2.5 v to 20 v, t min ? t max 108 120 108 120 db supply current (per amplifier) i sy no load 525 625 525 625 a t min ? t max 580 750 580 750 a supply voltage range v s operating range 2 20 2 20 v t min ? t max 2.5 20 2.5 20 v dynamic performance slew rate sr 0.05 0.15 0.05 0.15 v/s gain bandwidth product gbw 500 500 khz channel separation cs v o = 20 v p-p, f o = 10 hz 150 150 db noise performance voltage noise e n p-p 0.1 hz to 10 hz 0.3 0.3 v/p-p voltage noise density e n e n = 10 hz 17 17 nv/hz e n = 1 khz 15 15 nv/hz current noise density i n i n = 10 hz 20 20 fa/hz 1 guaranteed by cmr test.
op497 rev. e | page 4 of 16 absolute maximum ratings absolute maximum ratings apply to packaged parts. table 2. parameter rating supply voltage 20 v input voltage 1 20 v differential input voltage 1 40 v output short-circuit duration indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c 1 for supply voltages less than 20 v, the absolute maximum input voltage is equal to the supply voltage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case mounting conditions, that is, ja is specified for a device in socket for the pdip package, and ja is specified for a device soldered to the printed circuit board (pcb) for the soic package. table 3. package type ja jc unit 14-lead pdip (n-14) 76 33 c/w 16-lead soic (rw-16) 92 23 c/w 1/4 op497 v 2 2k? channel separation = 20 log () ? + 50? 50k ? ? + 1/4 op497 v 1 20v p-p @ 10hz v 1 v 2 /10,000 00309-004 figure 4. channel separation test circuit esd caution
op497 rev. e | page 5 of 16 typical performance characteristics t a = 25c, v s = 15 v, unless otherwise noted. 50 0 30 10 20 40 percentage of units input offset voltage (v) t a = 25c v s = 15v v cm = 0v ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 00309-006 figure 5. typical distributi on of input offset voltage 50 0 30 10 20 40 percentage of units input bias current (pa) t a = 25c v s = 15v v cm = 0v ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 0309-007 figure 6. typical distributi on of input bias current percentage of units 60 0 60 30 10 10 20 0 50 40 50 40 30 20 input offset current (pa) t a = 25c v s = 15v v cm = 0v 0 0309-008 figure 7. typical distribution of input offset current percentage of units 50 0 0.8 30 10 0.1 20 0 40 0.7 0.6 0.5 0.4 0.3 0.2 tcv os (v/c) v s = 15v v cm = 0v 0 0309-009 figure 8. typical distribution of tcv os 1k 100 10 temperature (c) +i b i os input current (pa) ?75 ?50 ?25 0 25 50 75 100 125 00309-010 v s = 15v v cm = 0v ?i b figure 9. input bias, offset current vs. temperature 70 0 15 30 10 ?10 20 ?15 60 40 50 10 5 0 ?5 ?i b +i b input bias current (pa) common-mode voltage (v) t a = 25c v s = 15v 0 0309-011 figure 10. input bias current vs. common-mode voltage
op497 rev. e | page 6 of 16 3 0 5 1 1 0 2 4 3 2 deviation from final value (v) time after power applied (minutes) t a = 25c v s = 15v v cm = 0v 0 0309-012 figure 11. input offset voltage warm-up drift 10 100 1k 10k 100k 1m 10m 10k 1k 100 10 source resistance ( ? ) effective offset voltage (v) t a = 25c 0 0309-013 balanced or unbalanced v s = 15v v cm = 0v figure 12. effective offset voltage vs. source resistance 100 1k 10k 100k 1m 10m 100m 100 10 1 0.1 source resistance ( ? ) effective offset voltage (v/c) 0 0309-014 balanced or unbalanced v s = 15v v cm = 0v figure 13. effective tcv os vs. source resistance 1k 100 10 1 voltage noise current noise t a = 25c v s = 2v to 20v voltage noise density (nv/ hz) current noise density (fa/ hz) frequency (hz) 1 10 100 1k 00309-015 figure 14. voltage noise density vs. frequency 10 1 0.1 0.01 source resistance ( ? ) total noise density (v/ hz) 1khz 10hz 100 1k 10k 100k 1m 10m t a = 25c v s = 2v to 20v 0 0309-016 figure 15. total noise density vs. source resistance 100 90 10 0% 1s 5mv 024681 0 time (seconds) noise voltage (100mv/div) v s = 15v t a = 25c 00309-017 figure 16. 0.1 hz to 10 hz noise voltage
op497 rev. e | page 7 of 16 100 ?40 10m 20 ?20 1k 0 100 80 40 60 1m 100k 10k 225 180 135 90 phase (degrees) open-loop gain (db) frequency (hz) gain phase v s = 15v c l = 30pf r l = 1m ? t a = 25c 0 0309-018 figure 17. open-loop gain and phase vs. frequency 10k 1k 100 11 load resistance (k ? ) open-loop gain (v/mv) v s = 15v v o = 10v 0 2 0 t a = 25c t a = 125c 0 0309-019 figure 18. open-loop gain vs. load resistance differential input voltage (10v/div) output voltage (v) ?15 ?10 ?5 0 5 10 15 r l = 2k ? v s = 15v v cn = 10v t a = 25c t a = 125c 0 0309-020 figure 19. open-loop gain linearity 160 0 1m 40 20 10 1 80 60 100 120 140 100k 10k 1k 100 frequency (hz) common-mode rejection (db) v s = 15v t a = 25c 0 0309-021 figure 20. common-mode rejection vs. frequency 160 0 40 20 80 60 100 120 140 1m 10 1 100k 10k 1k 100 power supply rejection (db) frequency (hz) 0 0309-022 ?psr +psr v s = 15v t a = 25c figure 21. power supply rejection vs. frequency 35 0 100k 15 5 1k 10 100 30 20 25 10k frequency (hz) output swing (v p-p) v s = 15v t a = 25c a vcl = +1 1% thd r l = 10k ? 0 0309-023 figure 22. maximum output swing vs. frequency
op497 rev. e | page 8 of 16 supply voltage (v) input common-mode voltage (v) (referred to supply voltages) + v s ?0.5 ?1.0 ?1.5 1.5 1.0 0.5 ?v s 0 5 1 0 1 5 t a = 25c 2 0 0 0309-024 figure 23. input common-mode voltage range vs. supply voltage 35 0 10k 15 5 100 10 10 30 20 25 1k load resistance ( ? ) output swing (v p-p) v s = 15v t a = 25c a vcl = +1 1% thd f o = 1khz 0 0309-025 figure 24. maximum output swing vs. load resistance supply voltage (v) output voltage swing (v) (referred to supply voltages) + v s ?0.5 ?1.0 ?1.5 1.5 1.0 0.5 ?v s 0 5 1 0 1 5 2 0 t a = 25c r l = 10k ? 0 0309-026 figure 25. output voltage swing vs. supply voltage supply voltage (v) supply current (per amplifier) (a) 700 200 0 5 10 15 20 600 500 400 300 no load 25c 125c 0 0309-027 figure 26. supply current (per amplifier) vs. supply voltage 1k 0.001 100k 1 0.01 10 0.1 1 100 10 10k 1k 100 00309-028 v s = 15v t a = 25c a v = +1 frequency (hz) impedance ( ? ) figure 27. closed-loop outp ut impedance vs. frequency 35 ?35 4 ?20 ?30 1 ?25 0 15 ?15 20 25 30 3 2 short-circuit current (ma) time from output short (minutes) t a = 25c t a = 125c t a = 25c v s = 15v output shorted to ground t a = 125c 0 0309-029 figure 28. short-circuit current vs. time at various temperatures
op497 rev. e | page 9 of 16 70 0 10k 30 10 100 20 10 60 40 50 1k load capacitance (pf) overshoot (%) 0 0309-030 v s = 15v t a = 25c a vcl = +1 v out = 100mv p-p figure 29. small-signal overshoot vs. load capacitance
op497 rev. e | page 10 of 16 applications information extremely low bias current makes the op497 attractive for use in sample-and-hold amplifiers, peak detectors, and log amplifiers that must operate over a wide temperature range. balancing input resistances is not necessary with the op497. high source resistance, even when unbalanced, only minimally degrades the offset voltage and tcv os . the input pins of the op497 are protected against large differential voltage by back-to-back diodes and current-limiting resistors. common-mode voltages at the inputs are not restricted and may vary over the full range of the supply voltages used. the op497 requires very little operating headroom about the supply rails and is specified for operation with supplies as low as 2 v. typically, the common-mode range extends to within 1 v of either rail. when using a 10 k load, the output typically swings to within 1 v of the rails. ac performance the ac characteristics of the op497 are highly stable over its full operating temperature range. figure 30 shows the unity-gain small signal response. extremely tolerant of capacitive loading on the output, the op497 displays excellent response even with 1000 pf loads (see figure 31 ). 10 90 100 0% 20mv 5s 00309-032 figure 30. small signal transient response (c load = 100 pf, a vcl = +1) 10 90 100 0% 20mv 5s 0 0309-033 figure 31. small signal transient response (c load = 1000 pf, a vcl = +1) 10 90 100 0% 2v 50s 00309-034 figure 32. large signal transient response (a vcl = +1) ?in +in 2.5k ? v + v out v? 2.5k ? 00309-031 figure 33. simplified schematic showing one amplifier
op497 rev. e | page 11 of 16 guarding and shielding to maintain the extremely high input impedances of the op497, care must be taken in circuit board layout and manufacturing. board surfaces must be kept scrupulously clean and free of moisture. conformal coating is recommended to provide a humidity barrier. even a clean pcb can have 100 pa of leakage currents between adjacent traces; therefore, use guard rings around the inputs. guard traces are operated at a voltage close to that on the inputs, as shown in figure 34 , so that leakage currents become minimal. in noninverting applications, connect the guard ring to the common-mode voltage at the inverting input. in inverting applications, both inputs remain at ground; therefore, the guard trace should be grounded. place guard traces on both sides of the circuit board. 1/4 op497 unity-gain followe r noninverting amplifier inverting amplifier b 8 a 1 pdip bottom view ? + ? + ? + 1/4 op497 1/4 op497 00309-035 figure 34. guard ring layout and connections open-loop gain linearity the op497 has both an extremely high gain of 2000 v/mv typical and constant gain linearity. this enhances the precision of the op497 and provides for very high accuracy in high closed-loop gain applications. figure 35 illustrates the typical open-loop gain linearity of the op497. output voltage (v) ?15 ?10 ?5 0 5 10 15 differential input voltage (10v/div) r l = 10k ? v s = 15v v cm = 0v t a = 25c t a = 125c 0 0309-036 figure 35. open-loop gain linearity
op497 rev. e | page 12 of 16 applications circuit precision absolute value amplifier the circuit in figure 36 is a precision absolute value amplifier with an input impedance of 30 m. the high gain and low tcv os of the op497 ensure accurate operation with microvolt input signals. in this circuit, the input always appears as a common- mode signal to the op amps. the cmr of the op497 exceeds 120 db, yielding an error of less than 2 ppm. +15 v 2 3 4 8 1 6 5 7 0v < v out < 10v d1 1n4148 c1 30pf d2 1n4148 1/4 op497 1/4 op497 ?15v v in r2 2k ? c3 0.1f r3 1k? r1 1k? c2 0.1f 00309-037 figure 36. precision absolute value amplifier precision current pump maximum output current of the precision current pump shown in figure 37 is 10 ma. voltage compliance is 10 v with 15 v supplies. output impedance of the current transmitter exceeds 3 m with linearity better than 16 bits. 2 3 1 7 8 5 6 4 ?15v +15v ? + v in 1/4 op497 1/4 op497 i out == = r5 v in 100 ? v in 10ma/v r3 10k ? r5 10k ? r4 10k ? r1 10k ? r2 10k ? i out 10ma 0 0309-038 figure 37. precision current pump precision positive peak detector in figure 38 , the c h must be of polystyrene, teflon?, or polyethylene to minimize dielectric absorption and leakage. the droop rate is determined by the size of c h and the bias current of the op497. 2 3 1 7 8 5 6 4 +15v 1n4148 2n930 reset 1/4 op497 1/4 op497 + + + ?15v v out 0.1f 0.1f c h v in 1k? 1k? 1k ? 1k? 00309-039 figure 38. precision positive peak detector simple bridge conditioning amplifier figure 39 shows a simple bridge conditioning amplifier using the op497. the transfer function is r r rr r vv f ref out ? ? ? ? ? ? ? ? + = the ref43 provides an accurate and stable reference voltage for the bridge. to maintain the highest circuit accuracy, r f should be 0.1% or better with a low temperature coefficient. 2 3 1 7 8 5 6 4 +5 v ref43 6 2 4 +5v r r r 2.5v r + r v out = v ref r r + rr 1/4 op497 1/4 op497 v ref r f v out ?5v r f () 00309-040 figure 39. simple bridge conditioning amplifier using the op497
op497 rev. e | page 13 of 16 nonlinear circuits due to its low input bias currents, the op497 is an ideal log amplifier in nonlinear circuits, such as the squaring amplifier and square root amplifier circuits shown in figure 40 and figure 41 . using the squaring amplifier circuit in figure 40 as an example, the analysis begins by writing a voltage loop equation across transistors q1, q2, q3, and q4. ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? s4 ref t4 s3 o t3 s2 in t2 s1 in t1 i i inv i i iinv i i inv i i inv all the transistors in the mat04 are precisely matched and at the same temperature; therefore, the i s and v t terms cancel, giving 2ini in = ini o + ini ref = in ( i o i ref ) exponentiating both sides of the thick equation lead to () ref in o i i i 2 = op amp a2 forms a current-to-voltage converter which results in v out = r2 i o . substituting (v in /r1) for i in and the previous equation for i o yields 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? = r1 v i r2 v in ref out 1 2 3 6 7 5 c1 100pf v+ 2 3 8 1 4 v? 6 5 7 i o 9 8 10 q1 q3 q2 14 12 q4 13 i ref mat04 1/4 op497 1/4 op497 a2 a1 i in v in r1 133k ? ?15v r3 50k ? r4 50k? c2 100pf r2 33k ? v out 00309-041 figure 40. squaring amplifier a similar analysis made for the square root amplifier circuit in figure 41 leads to its transfer function ( ) ( ) r1 iv r2v refin out = in these circuits, i ref is a function of the negative power supply. to maintain accuracy, the negative supply should be well regulated. for applications where very high accuracy is required, a voltage reference can be used to set i ref . an important consideration for the squaring circuit is that a sufficiently large input voltage can force the output beyond the operating range of the output op amp. resistor r4 can be changed to scale i ref , or r1 and r2 can be varied to keep the output voltage within the usable range. 1 2 3 6 7 5 v+ 2 3 8 1 4 6 5 7 i o 9 8 10 q1 q3 q2 14 12 q4 13 mat04 c2 100pf 1/4 op497 1/4 op497 v out r2 33k? i ref i in c1 100pf ?15v v? r5 2k? r3 50k ? r4 50k ? v in r1 33k? 0 0309-042 figure 41. square root amplifier unadjusted accuracy of the square root circuit is better than 0.1% over an input voltage range of 100 mv to 10 v. for a similar input voltage range, the accuracy of the squaring circuit is better than 0.5%.
op497 rev. e | page 14 of 16 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 42. 14-lead plastic dual in-line package [pdip] narrow body (n-14) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 43. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches)
op497 rev. e | page 15 of 16 ordering guide model temperature range package description package option op497fp ?40c to +85c 14-lead plastic dual in-line package [pdip] n-14 op497fpz 1 ?40c to +85c 14-lead plastic dual in-line package [pdip] n-14 op497gp ?40c to +85c 14-lead plastic dual in-line package [pdip] n-14 op497gpz 1 ?40c to +85c 14-lead plastic dual in-line package [pdip] n-14 op497fs ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 op497fs-reel ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 op497fsz 1 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 op497fsz-reel ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 op497gs ?40c to +85c 16-lead standard small outline package [soic_w rw-16 op497gs-reel ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 op497gsz 1 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 OP497GSZ-REEL 1 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 1 z = rohs compliant part.
op497 rev. e | page 16 of 16 notes ?1991C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00309-0-2/09(e)

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